Qualcomm Targets AI Memory Bottleneck With HPC Technology Roadmap

Qualcomm’s High Bandwidth Compute (HPC) technology is designed to address AI inference “memory wall” constraints by combining compute and memory co-design. The first generation is expected to ship in 2027, with a second generation planned for 2028. Qualcomm is expanding its data-center strategy beyond HPC, with the Dragonfly C1000 server CPU targeted for commercial availability in the second half of 2028 and parallel Arm and RISC-V processor roadmaps. The company is building a broader AI ecosystem through its Modular software acquisition, a Hugging Face partnership and Alphawave’s custom-silicon and networking assets, aiming to support AI deployment from cloud data centers to edge devices.

Qualcomm NASDAQ: QCOM is positioning its newly announced High Bandwidth Compute, or HPC, technology as a way to address memory-bandwidth constraints in artificial intelligence data centers, while also expanding its server CPU, custom silicon and software efforts. During a fireside chat, Durga Malladi, Qualcomm’s executive vice president of technology planning and edge data center, said the company’s HPC development program had been underway for years before its public introduction. He said Qualcomm identified a growing mismatch around 2021 between rapidly increasing compute capacity in data-center racks and more modest growth in memory bandwidth.

“It eventually will lead to a memory wall,” Malladi said, referring particularly to the decode portion of AI inference workloads, where he said additional compute alone does not resolve performance constraints without greater memory bandwidth.

Malladi described HPC as a compute-and-memory co-design approach rather than a standalone memory technology. Qualcomm does not manufacture the DRAM stacks used in the architecture, he said, but provides the compute die and system design while working with memory vendors and foundry partners including TSMC.

Qualcomm has said its first-generation HPC product is expected to be commercial and shipping in 2027, with a second generation planned for 2028. Malladi said silicon for the first generation has returned to Qualcomm’s lab and is progressing well, though the company did not provide a specific date for further validation disclosures. The executive reiterated Qualcomm’s previously stated performance targets, including a claimed sixfold improvement in tokens per second per watt relative to high-bandwidth memory, or HBM. He also said Qualcomm’s architecture is designed to provide memory bandwidth in the “hundreds of terabytes per second,” compared with approximately 21 to 22 terabytes per second for HBM today, according to his remarks. He said the company sees an advantage versus SRAM in total cost of ownership because SRAM’s speed comes with a larger area requirement, potentially requiring more racks for equivalent workloads. Malladi added that Qualcomm has received interest from memory suppliers and hyperscalers, including discussions on supply and potential product configurations. HPC can be offered as a standalone component alongside a customer’s existing CPU and AI accelerator, according to Malladi. Customers may also adopt Qualcomm’s CPU, AI accelerator and HPC technology together. Qualcomm expects early adopters to use the first generation, while potentially broader volume demand could develop with the 2028 second generation. Malladi said HPC is targeted at decode workloads, while prefill remains predominantly co...